If P is Passivation, Q is n-well implant, R is metallization and S is soruce/drain diffusion, then the order in which they are carried out in a standard n-well CMOS fabrication process, is

At 300 K, for a diode current of 1 mA, a certain germanium diode requires a forward bias of 0.1435V, whereas a certain silicon diode requires a forward bias of 0.718 V. Under the conditions stated above, the closest approximation of the ratio of reverse saturation current in germanium diode to that in silicon diode is

A Silicon PN junction at a temperature of 20°C has a reverse saturation current of 10 pico-Amperes (pA). The reverse saturation current at 40°C for the same bias is approximately

n-type silicon is obtained by doping silicon with

The drain current of MOSFET in saturation is given by I_D = K (V_GS-V_T) where K is constant. The magnitude of the transconductance g_m is

For an n-channel enhancement type MOSFET, if the source is connected at a higher potential than that of the bulk, (i.e. V_SB > 0) the threshold voltage V_T of the MOSFET

The silicon sample with unit cross-sectional area shown below is in thermal equilibrium. The following information is given: T=300K, electronic charge=1.6x10^-19C, thermal voltage=26mV and electron mobility = 1350cm²/V-s

The magnitude of the electric field at x = 0.5 $\mu$m is

The source of a silicon (n_i = 10¹⁰ per cm³) n – channel MOS transistor has an area of 1 sq ^{_{$\mu m$}} and a depth of 1 ^{_{$\mu m$}}. If the dopant density in the source is 10¹⁹/cm³, the number of holes in the source region with the above volume is approximately.

The measured trans conductance gm of an NMOS transistor operating in the linear region is plotted against the gate voltage VG at a constant drain voltage V_D. Which of the following figures represents the expected dependence of g_m on V_G?

The silicon sample with unit cross-sectional area shown below is in thermal equilibrium. The following information is given: T=300K, electronic charge=1.6x10^-19C, thermal voltage=26mV and electron mobility = 1350cm²/V-s

The magnitude of the electron drift current density at x = 0.5 $\mu$m is

A p ⁺n junction has a built-in potential of 0.8 V. The depletion layer width at a reverse bias of 1.2V is 2 $\mu$m. For a reverse bias of 7.2 V, the depletion layer width will be

When the gate-to-source voltage (VGS) of a MOSFET with threshold voltage of 400 mV, working in saturation is 900 mV, the drain current in observed to be 1 mA. Neglecting the channel width modulation effect and assuming that the MOSFET is operating at saturation, the drain current for an applied VGS of 1400 mV is

The action of a JFET in its equivalent circuit can best be represented as a

Find the correct match between Group 1 and Group 2:

Group 1 Group 2 E. Varactor diode 1. Voltage reference F. Pin diode 2. High frequency switch G. zener diode 3. Tuned circuits H. Schottky diode 4. Current controlled attenuator

The given figure is the voltage transfer characteristic of

Consider the following statements S1 and S2 S1 : At the resonant frequency, the impedance of a series RLC circuit is zero. S2 : In a parallel GLC circuit, increasing the conductance G results in increase in its Q factor. Which one of the following is correct?

Directions: Consider a silicon p - n junction at room temperature having the following parameters: Doping on the n-side = 1 x 10¹⁷ cm^-3 Depletion width on the n-side = 0.1 $\mu$m

The built-in potential of the junction Depletion width on the p −side = 1.0 $\mu$m Intrinsic carrier concentration = 1.4 x 10¹⁰ cm^-3 Thermal voltage = 26 mV Permittivity of free space = 8.85 x 10^-14 F cm^-1 Dielectric constant of silicon = 12 The built-in potential of the junction

Directions : Consider a silicon p - n junction at room temperature having the following parameters: Doping on the n-side = 1 x 10¹⁷ cm^-3 Depletion width on the n-side = 0.1 $\mu$m Depletion width on the p −side = 1.0 $\mu$m Intrinsic carrier concentration = 1.4 x 10¹⁰ cm^-3 Thermal voltage = 26 mV Permittivity of free space = 8.85 x 10^-14 F cm^-1 Dielectric constant of silicon = 12

The peak electric field in the device is