Computer Organization
Description: System Architecture Design Computer Organization and ArchitectureComputer Architect | |
Number of Questions: 30 | |
Created by: Darshan Khurana | |
Tags: System Architecture Design Computer Organization and Architecture Computer Architect |
In which of the following logic gates, the output is OFF only when both the inputs are ON?
In which of the following, each operand datum occupies one byte in 8086 processor?
In which, a latching circuit timed with the clock signal would most likely have to be connected to the IGFET gate to ensure full discharge of the capacitor when the comparator's output goes high?
In which of the following, the output is ON only when any one of the inputs were ON, and output is OFF if both inputs are at the same logic?
Which of the following accepts three 1 bit inputs and generate a Sum and a Carry output?
Which of the following flags is set to 1, if the low-order 8 bits of the result contains an even number of 1's otherwise it is cleared in 8086 processor?
Which should be used to clock a latch and hold circuit such as a 74LS245 or 74LS373?
Which of the following line indicates that the 8085 micro processor is going to send data away from itself?
Which line indicates that the 8085 micro processor is expecting data to be fed to it?
Which of the following logic circuits takes n inputs lines and provides pow(2,n) output lines?
In which circuit, if any of the input resistor is different, the input voltages would have different degrees of effect on the output and the output voltage would not be a true sum?
Which of the following instructions permit the accumulator to access groups of data bytes, as may be necessary with long precision arithmetic in 8085 processor?
Which of the following logic circuits takes data in parallel from several sources and send the data out serially on one line in a time sequence?
Which indicates when two numbers are equal or which number is greater than the other?
Which of the following instructions provides a quick means of adding one to the contents of a register or memory location in 8085 processor?
Which of the following instructions provides a means of subtracting 1 from the contents of a register or a memory location in 8085 processor?
Which of the following instructions perform a logical AND function between the specified byte, either in a register or in the address contained in the H and L registers, and the contents of the accumulator?
In which of the following, the highest value input digit is encoded and any other active input is ignored?
In which circuit, all the flip-flops are simultaneously triggered from the same clock input?
Which of the following is used for error detection in digital codes?
Which instructions perform inclusive Or's between the specified byte, either in a register or in the address contained in the H&L registers and the contents of the accumulator in 8085 processor?
Which situates various bits to form masks or generate output data via the SOD line in 8085 processor?
Which instructions perform Exclusive Or's functions between a specified byte, either in a register or in a byte contained in the address in the H&L registers, and the contents of the accumulator in 8085 processor?
Which of the following instructions compares the contents of the accumulator to a fixed value provided by the second byte of the instructions?
In which of the following circuits, the mode control may control the direction of shifting in some real devices and the data will be shifted one bit position for each clock pulse?
Which of the following flags is set to 1 if the result is zero, and 0 if the result is non zero in 8086 processor?
Which instruction permits the system to examine the interrupt mask by loading into the A register a byte which defines the condition of the mask bits for the maskable interrupts in 8085 processor?
In which of the following, the complement output of a ring counter is fed back to the input instead of the true output?
Which instruction includes the carry flag in the circle in 8086 processor?
In which of the following circuits, the high-to-low transition of the comparators's output will cause the shift register to load whatever binary count is being output by the counter, thus updating the ADC circuit's output?