Quadrature oscillators provide two signals, which are at 90 degree out of phase.

Band gap is the energy gap of the electrons in valance band and inner band. It is 1.10 ev.

Yes both the statements (1) and (2) are correct.

The junction layers at BE, BC and the portion at CE offers capacitive effect to the flow of electrons in BJT when properly exited. This capacitive effect becomes prominently high to reduce the flow of electrons during the high frequency signal's cycle time. Due to this, the gain falls (current reduces due to decrease in flow of electrons from C to E).

In this filter, only a specified filtering is done that is only specified band of frequencies of the signal is allowed. This is done by allowing specific low frequencies and then specific high frequencies. This is achieved by cascading high and low pass filters.

The response of the complete design is similar to band reject filter, and if a two input adder is connected at the outputs of the two filters then the complete system will behave as Band reject filter exactly.

Boron is pentavelant and has capacity to donate required electrons to silicon to make it N type.

By reducing the transition period of the LPF, one can reduce the lock range because lock range frequencies are those frequencies, which lie in the transition band of the filter.

Both options (1) and (3) are correct.

Output offset characteristic is defined as: it is the voltage (may be 10 mv) produced by the OPAMP when its both inputs are grounded. This is not a faulty condition, rather some time it is required  in some applications.

Clock signal is concurrently applied to the each flip flop and so the output from each flip flop is simultaneously. Hence, each flip flop will have same i.e. 10 msec.

Ripple counter is asynchronous counter, i.e. output of each flip flop is a clock to next flip flop. In 4 bit ripple counter, no. of flip flop is 4. Maximum delay is 40 msec, the delay propagates from first flip flop to last flip flop in 4 clocks. So, the delay from each flip flop is 40/4 = 10 msec. Delay in first flip flop + delay in second flip flop and so on.

CMOS has the highest delay as compared to devices given in other options.

Delay is propagated from first stage to second. Since all four devices are connected to first stage only, so the delay will remain at its nominal value i.e. it will not be affected.

Second output should be shifted by 90 degree phase. Cosine changes to Sine when shifted by 90 degree. It is the correct answer.

The OPAMP is in amplification mode to provide the required current gain to remove the damping effect on the output so that the output will have a constant amplitude and constant frequency output. This is sustained oscillations.

The RC section works as tank circuit for the signal coming from the output of the integrator and so the integrator output goes into sinusoidal oscillations. So, this portion provides the sinusoidal wave in quadrature oscillator.

In saturation region, the output provides the maximum possible output when output is cut off, i.e. the voltage equal to Vcc or Vsat. during +ve cycle of sine wave at input. And -Vcc or -Vsat during -Ve cycle of sine wave. So, it will be a square wave of input frequency and Vsat amplitude.

Yes, all the options 1, 2 and 3 are correct.