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Online Test 2 - Digital Logic

Description: GATE Exam Online practice test - Digital Logic
Number of Questions: 25
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Tags: digital logic GATE CS
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A binary number is given as 1101. Find the 2's complement of this number. Which option will give correct answer of 2's complement of 1101?

  1. 110100

  2. 001101

  3. 110111

  4. 00 0011

Show answer
Correct Option: D
Explanation:

ExplanationIn six binary digit form number is

The total number of Boolean functions that can be generated by n variables is equal to

  1. $2^{2^n}$

  2. $2^{2n}$

  3. $2^{n-1}$

  4. $2^{n-2}$

Show answer
Correct Option: A
Explanation:

 for n independent Boolean variables, each taking one particular Boolean value, there are 2n different possible combinations. A Boolean function has to assign one Boolean value to each one of these combinations. This brings the number of different possible Boolean functions of n variables to a total of  $2^{2^n}$

Calculate the least number of 2-input NAND gates that are required to implement the Boolean function z = A$\bar B$C.

  1. Two

  2. Three

  3. Five

  4. Six

Show answer
Correct Option: C
Explanation:

 Z = A$\bar B$C=  $\dfrac{(AC)(\bar B)}{\overline {AC} + B}$Let F $\therefore$ 5 NAND gates required.

Find the value of x and y in the given decimal equivalent relationship. (28)x = (50)y.

  1. x = 16, y = 8

  2. x = 8, y = 4

  3. x = 8, y = 16

  4. x = 4, y = 2

Show answer
Correct Option: A
Explanation:

2x + 8 = 5y.x = $\dfrac{5y - 8}{2}$………….. (1)From the above option, if y = 8, x = 16.So the equivalent relationship(28)16 = (50)8

Consider a 4-bit ripple counter and a 4-bit synchronous counter made using flip-flops. Propagation delay = 10 nano-seconds. R = worst case delay in the ripple counter, S = worst case delay in the synchronous counter. Which of the following options is correct?

  1. R = 10 ns, S = 40 ns

  2. R = 40 ns, S = 10 ns

  3. R = 10 ns, S = 30 ns

  4. R = 30 ns, S = 10 ns

Show answer
Correct Option: B
Explanation:

Propagation delay in 4-bit ripple counter = 4 Td = 40 ns. Propagation delay in synchronous counter = Td = 10 ns.

The logic realised by the circuit as shown in the figure below is

  1. F = A.C

  2. F = A + C

  3. F = A$\oplus$B$\oplus$C

  4. F = A$\oplus$C

Show answer
Correct Option: D
Explanation:
S1(A) S0(B) F
0 0 C
0 1 C
1 0 $\bar C$
1 1 $\bar C$

 F is not dependent on B.F = $\bar A$C + A$\bar C$ = A$\oplus$C.

Choose the correct one from among the alternatives A, B, C, D after matching an item from Group 1 with the must appropriate item in Group 2.

Group 1 Group 2
P : Shift Register 1. Frequency division
Q : Counter 2. Addressing memory chips
R : Decoder 3. Serial to parallel data

  1. P - 3, Q - 2, R - 1

  2. P - 3, Q - 1, R - 2

  3. P - 2, Q - 1, R - 3

  4. P - 1, Q - 2, R - 2

Show answer
Correct Option: B
Explanation:

Shift register is used as serial and parallel converter and counter is used as frequency division. Decoder is used as addressing memory chips.

Find the output Y (A, B, C) in the figure, A, B and C are Boolean variables.

  1. $\overline {AB}$+ $\bar A$BC

  2. A + BC

  3. $\bar A$$\bar B$ + BC

  4. (AB + A$\bar B$) C

Show answer
Correct Option: C
Explanation:

Explanation Y = $\bar A$$\bar B$I0 + $\bar A$BI1 + A$\bar B$I2 + ABI3= $\bar A$$\bar B$×1 + $\bar A$BC + A$\bar B$×0 + ABC= $\bar A$$\bar B$ + $\bar A$BC + ABC= $\bar A$$\bar B$ + BC

A gate having two inputs (A and B) and one output (Y) is implemented using a 4-to-1 multiplexer as shown in the figure below. A1 (MSB) and A0 are the control bits and I0 - I3 are the inputs to the multiplexer. The gate is

  1. NAND

  2. NOR

  3. XOR

  4. OR

Show answer
Correct Option: D
Explanation:

A1 = A, A0 = B, I0 = I2 = A, I1 = I3 = BY = $\bar A_1$$\bar A_0$I0 + $\bar A_1$A0 I1 + A1$\bar A_0$I2 + A1 A0 I3Y = $\bar A$$\bar B$A + $\bar A$BB + A$\bar B$A + ABBY = $\bar A$B + A$\bar B$ + AB = $\bar A$B + A = A + B

How many 2 : 2 : 1 mux are required to construct 4 : 4 : 1 mux?

  1. 2

  2. 4

  3. 3

  4. 6

Show answer
Correct Option: C
Explanation:

An X-Y flip flop whose characteristic table is given below is to be implemented using a J-K flip-flop.

X Y $Q{n+1}$
0 0 1
0 1 $Q_n$
1 0 $\bar Q_n $
1 1 0

  1. J = X, K = $\bar Y$

  2. J = $\bar X$, K = Y

  3. J = Y, K = $\bar X$

  4. J = $\bar Y$, K = X

Show answer
Correct Option: D
Explanation:

J-K flip flop excitation table is given as, So, (d) option is correct. Given truth table: Table 2 (J and K column constructed using table 1) J =$\bar Y$ K = X

Which of the following statements is correct?

  1. A flip-flop is used to store 1-bit of information.
  2. Race around condition occurs in a J-K flip-flop when both inputs are 1.
  3. Master slave configuration is used in flip-flops to store 2-bits of information.
  4. A transparent latch consists of a D-type flip-flop. Select the correct answer using the codes given above.

  1. 1,2 and 3

  2. 1, 3 and 4

  3. 1, 2 and 4

  4. 2, 3 and 4

Show answer
Correct Option: C
Explanation:

 According to the definition of flip-flop, it consists of a latch used to store 1-bit of information. Race around condition occurs in J-K flip-flop, if the output continuously toggles. D-type flip-flop's output is equal to input.

What is the minimum number of gates required to implement the Boolean function (AB + C) if we have to use only 2-input NOR gates?

  1. 2

  2. 3

  3. 4

  4. 5

Show answer
Correct Option: B
Explanation:

.

The circuit in the figure below has 4 boxes each described by inputs P, Q, R and output Y, Z with Y = P$\oplus$Q$\oplus$R Z = RQ + $\bar P$R + Q$\bar P$

The circuit acts as a

  1. 4-bit adder giving P + Q

  2. 4-bit subtractor giving P – Q

  3. 4-bit subtractor giving Q – P

  4. 4-bit adder giving P + Q + R

Show answer
Correct Option: B
Explanation:

Explanation Let P = 1011 and Q = 1001. Given Yn = Pn $\oplus$Qn$\oplus$RnZn = Rn Qn $\oplus$ $\bar p_n$ Rn $\oplus$ Qn$\bar p_n$

Pn Qn Rn Zn Yn
1 1 0 0 0
1 0 0 0 1
0 0 0 0 0
1 1 0 0 0
0

                      Where, Y = P + Q + RZ = RQ + $\bar PR$ +  $Q\bar P$   From the circuit given, we have Rn + 1 = Zn, 1$\le$n$\le$3Z4 = Ys (MSB). Hence, the output is 00010, which shows a 4-bit subtractor P – Q. 

In the figure given below, U1 is a 4-bit synchronous centre with synchronous clear. Q0 is the LSB and Q3 is the MSB of the output. The circuit represents a

  1. mod 2 counter

  2. mod 3 counter

  3. mod 4 counter

  4. mod 5 counter

Show answer
Correct Option: B
Explanation:

||||| |---|---|---|---| |

Q3
|
Q2
|
Q1
|
Q0
| |
0
|
0
|
0
|
0
| |
0
|
0
|
0
|
1
| |0|0|1|0| |0|0|1|1| |
0
|
1
|
0
|
0
|  After that it is clear, so it represents mod 3 counter

Consider a vending machine which sells product ‘A’ and ‘B’ and has push buttons X1 and X2. On pressing the button of the vending machine, the price of either product is displayed in a seven – segment display. Case: No buttons pressed - ‘0’ is displayed signifying Rs.’0’. Case: If only X1 is pressed - ‘2’ is displayed signifying Rs. 2. Case: If only X2 is pressed - ‘5’ is displayed signifying Rs. 5. If both X1 and X2 are pressed - ‘E’ is displayed signifying error.

The figure given below shows the name of the segment in the seven – segment display and the glow of the display for ‘0’, ‘2’, ‘5’, and ‘E’. If segments ‘a’ to ‘g’ are considered as functions of X1 and X2, then which of the following is true?

  1. g = $\bar P_1$ + P2

  2. g = P1 + P2

  3. g = $\bar P_1$+ P2

  4. g = P1 + P2

Show answer
Correct Option: B
Explanation:

0 = $\bar X_1\bar X_2$, 2 = X1$\bar X_2$,  5 = X2$\bar X_1$,  E = X1X2 G = 2 + 5 + E = X1 + X2 a = 1b = 0 + 2 = $\bar X_2$c = 0 + 5 = $\bar X_1$d = 1e = 0 + 2 + E = X1 + X2 f = 0 + 5 + E = X1 X2

If the functions W, X, Y, Z are as follows $W = R + \bar PQ + \bar RS;\ X = PQ\bar R\bar S + \bar P\bar Q\bar R\bar S + P\bar Q\bar R; Y = RS + \overline{PR + P\bar Q + \bar P \bar Q}$ and $Z = R + S + \overline{PQ + P\bar Q\bar R + \bar P \bar Q \bar S}$. Then

  1. $W = Z, X = \bar Z$

  2. $W = Z, X = Y$

  3. $W = Y$

  4. $W = Y = \bar Z$

Show answer
Correct Option: A
Explanation:

$W = R + \bar PQ + \bar RS$ $X = PQ\bar R\bar S+\bar P\bar Q\bar R\bar S+ \bar P\bar Q\bar R\bar S$ $Y = RS + \overline{PR + P\bar Q + \bar P \bar Q} = RS + \bar PR.\overline{PR}.\overline{P\bar Q}\overline{\bar P\bar Q}=RS + (\bar P + bar R)(\bar P + Q)(P + Q) = RS + (\bar P + \bar RQ)(P +Q) = RS + \bar pQ + \bar RPQ + Q\bar R$

$Z=R+S+\overline{PQ+\bar P.\bar Q.\bar R + P\bar Q.\bar S}=R+S+\overline{PQ}.\overline{\bar p\bar Q\bar S} = R + S + (\bar P + Q)(P+Q+R).(\bar P + Q + S)= R + S+ (\bar P + \bar Q(Q +S)).(P+ Q+ R)= R +S +\bar P Q + \bar P R+\bar QPS + \bar QRS(P + Q + R) . (\bar P + Q + S)= R + S + (\bar P + \bar Q (Q + S)) . (P + Q + R)= R + S + \bar P Q + \bar PR + \bar PPS + \bar PRS $

From above, we can conclude that $W = Z, X =\bar Z$

The dual of the expression derived in the following table is

$C$ $\bar C$
$\bar A$ $\bar B$ 0 0
$\bar A$ $ B$ 1 1
$\bar A$ $\bar B$ 1 1
$A$ $\bar B$ 0 1

  1. $X = AC + B$

  2. $X = A\bar B$

  3. $X = AB\bar C$

  4. $X = AB + ABC + A\bar B$

Show answer
Correct Option: A
Explanation:

.

P and Q are two numbers represented in signed two’s complement as 11101101 and 11100110 respectively. Calculate Q – P as signed two’s complement form.

  1. 1 0 0 0 0 0 1 1 1

  2. 0 0 0 0 0 1 1 1

  3. 1 1 1 1 1 0 0 1

  4. 1 1 1 1 1 1 0 0 1

Show answer
Correct Option: C
Explanation:

Complementing the output (Q – P) results in a correct  option.

P and Q are two numbers represented in signed two’s complement as 11101101 and 11100110 respectively. Calculate P – Q as signed two’s complement form.

  1. 00000111

  2. 0000 1001

  3. 0011 1001

  4. 1100 1100

Show answer
Correct Option: A
Explanation:

$ P = 111 0111 01 $ $\bar P = 000 10010 $ $\bar P+ 1 = 000 100 11 \qquad Q = 11100110$ $\bar Q = 000 11 001 \qquad \bar Q + 1 = 000 11 010 \qquad Q – P = 00011010$ $P – Q = 00010011$

Consider the following logic circuit of two - four decoders. For each of the decoder F0 = 1 when i1 = 0, i2 = 0 F1 = 1 when i1 = 1, i2 = 0 and so on. Which of the following is the result of (x, y, z)?

  1. $\bar x \bar y + \bar x \bar y \bar z$

  2. $xyz$

  3. $[xy +\bar x\bar y]z$

  4. 1

Show answer
Correct Option: D
Explanation:

$g(x, y, z) = F0 + F1 = i\bar z + i\bar z $

x y z
0 0 F0
0 1 F1
1 0 F2
1 1 F3

$I_1 = F_2. F_3 = x\bar y.xy = 0g(x,y,z) =\bar z + z = 1$

The Boolean expression for the truth table shown is

A B C F
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 0

The expression for the above truth table is

  1. $ B (A + C) (\bar A+ \bar C) $

  2. $ B (A + \bar C) (\bar A + C)$

  3. $\bar B (A + \bar C) (\bar A + C)$

  4. $\bar B (A + C) (\bar A + \bar C)$

Show answer
Correct Option: A
Explanation:

 

$=\bar ABC + AB\bar C= B (A\bar C + \bar AC)=B (A + C)(\bar A + \bar C)$

Following is the Boolean expression for one truth table of an unknown function.

A B C F
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 0

If the above function is implemented using D flip-flop, then

  1. $ D_A = \bar AB + \bar BC + AC$

  2. $ D_A = A \bar B \bar C + BC$

  3. $ D_A = ABC + AB$

  4. $ D_A = A \bar B + C \bar A$

Show answer
Correct Option: B
Explanation:

$J_A = \bar ABC + AB\bar C = B (\bar C + A\bar C) $ $K_A = A + \bar A\bar C$
$D = A\bar B\bar C + BC $

For the given Boolean expression for one truth table of an unknown function.

A B C F
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 0
1 1 1 0

The output recycles after the last state. If the above function is implemented using J-K flip flop then,

  1. $ J_A = B(\bar AC + A\bar C), K_A = A + \bar A\bar C$

  2. $ J_A = \bar B(A\bar C +\bar AC), K_A = A + \bar A\bar B$

  3. $ J_A = B(\bar AC + A\bar C), K_A = B + AC$

  4. $ J_A = \bar C(\bar AB + B\bar A), K_A = A + \bar A\bar C$

Show answer
Correct Option: A
Explanation:
A B C F JA KA D
0 0 0 1 X 1 0
0 0 1 0 0 X 0
0 1 0 0 0 X 0
0 1 1 0 1 X 1
1 0 0 1 X 0 1
1 0 1 1 X 1 0
1 1 0 0 0 X 0
1 1 1 0 1 x 1

$J_A = \bar ABC + AB\bar C = B (\bar AC + A\bar C)$

$K_A = A + \bar A\bar C $

$D = A\bar B\bar C + BC$

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