Test 3 Digital Logic | Computer Science(CS)

Description: GATE Previous year Topic Wise Questions and Answers | Digital Logic
Number of Questions: 26
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Assuming all numbers are in 2's complement representation, which of the following numbers is divisible by 11111011?

  1. 11100111

  2. 11100100

  3. 11010111

  4. 11011011


Correct Option: A
Explanation:

We can't judge the no's in 2's complement first we need to convert them in decimal Given no. $ 11111011 \rightarrow 00000101 = 5 $
$ 11100111 \rightarrow 00011001 = 25 $ $ 11100100 \rightarrow 00011100 = 28 $
$ 11010111 \rightarrow 00101001 = 41 $ $ 11011011 \rightarrow 00100101 = 37 $

From all only option (1) is divisible by 5. Shortcut: To convert 2's complement no. directly into original binary, we should complement all the digits from MSB till the last one (1). Keep the last 1 from the LSB as it is. Observe the example.

he sum of the number of times each literal appears in the expression. For example, the literal count of (xy + xz') is 4. What are the minimum possible literal counts of the product-of-sum and sum-of product representations respectively of the function given by the following Karnaugh map? Here, X denotes “don't care”

  1. (11, 9)

  2. (9, 13)

  3. (9, 10)

  4. (11, 11)


Correct Option: A
Explanation:

Consider the following circuit composed of XOR gates and non-inverting buffers

enter image description here

The non-inverting buffers have delays d1 = 2 ns and d2 = 4 ns as shown in the figure. Both XOR gates and all wires have zero delay. Assume that all gate inputs, outputs and wires are stable at logic level 0 at time

  1. If the following waveform is applied at input A, how many transition(s) (change of logic levels) Occur (s) at B during the interval from 0 to 10 ns?

enter image description here

  1. 1

  2. 2

  3. 3

  4. 4


Correct Option: C
Explanation:

Due to delays s1= 2 & s2=4 the transistions would occur at time1, 2 & 4.

Time Input (A) Output (B)
0 1 0
I 1 1 0 Transition
II 2 1 0 Transition
III 4 0 1 Transition

So total 3 transistions

You are given a free running clock with a duty cycle of 50% and a digital waveform f which changes only at the negative edge of the clock. Which one of the following circuits (using clocked D flip-flops) will delay the phase of f by 180°?


Correct Option: B
Explanation:

Consider the circuit above. Which one of the following options correctly represents f (x, y, z)?

  1. $x\bar{z}+xy+\bar{y}z$$

  2. $x\bar{z}+xy+\overline{yz}$

  3. $xz+xy+\overline{yz}$

  4. $xz+x\bar{y}+\bar{y}z$


Correct Option: A
Explanation:

We consider the addition of two $2's$ complement numbers $ b_{n-1}b_{n-2}\dots b_{0}$ and $a_{n-1}a_{n-2}\dots a_{0}$. A binary adder for adding unsigned binary numbers is used to add the two numbers. The sum is denoted by $ c_{n-1}c_{n-2}\dots c_{0}$ and the carry-out by $ c_{out}$. Which one of the following options correctly identifies the overflow condition?

  1. $ c_{out}\left ( \overline{a_{n-1}\oplus b_{n-1}} \right )$

  2. $ a_{n-1}b_{n-1}\overline{c_{n-1}}+\overline{a_{n-1}b_{n-1}}c_{n-1}$

  3. $ c_{out}\oplus c_{n-1}$

  4. $ a_{n-1}\oplus b_{n-1}\oplus c_{n-1}$


Correct Option: C
Explanation:

Binary adder generates C out only if

Consider a Boolean function $ f(w,x,y,z)$. Suppose that exactly one of its inputs is allowed to change at a time. If the function happens to be true for two input vectors $ i_{1}=\left \langle w_{1}, x_{1}, y_{1},z_{1}\right \rangle $ and $ i_{2}=\left \langle w_{2}, x_{2}, y_{2},z_{2}\right \rangle $ , we would like the function to remain true as the input changes from $ i_{1}$ to $ i_{2}$ ($ i_{1}$ and $ i_{2}$ differ in exactly one bit position) without becoming false momentarily. Let $ f(w,x,y,z)=\sum (5,7,11,12,13,15)$ . Which of the following cube covers of $f$ will ensure that the required property is satisfied?

  1. $ \overline{w}xz,wx\overline{y},x\overline{y}z,xyz,wyz$

  2. $ wxy, \overline{w}xz,wyz$

  3. $ wx\overline{y} \overline{z}, xz, w\overline{x}yz$

  4. $ wx\overline{y}, wyz, wxz, \overline{w}xz, x\overline{y}z, xyz$


Correct Option: A
Explanation:

Consider numbers represented in 4-bit gray code. Let h3 h2 h1 h0 be the gray code representation of a number n and let g3 g2 g1 g0 be the gray code of (n + 1) (modulo 16) value of the number. Which one of the following functions is correct?

  1. g0 (h3 h2 h1 h0) = $\sum$1, 2, 3, 6, 10, 13, 14, 15

  2. g0 (h3 h2 h1 h0) = $\sum$4,9,10,11,12,13, 14,15

  3. g0 (h3 h2 h1 h0) = <$\sum$2, 4,5, 6, 7,12,13,15

  4. g0 (h3 h2 h1 h0) = $\sum$0,1,6, 7,10,11,12,13


Correct Option: B
Explanation:

Given two three bit numbers a2 a1 a0 and b2 b1 b0 and c, the carry in, the function that represents the carry generate function when these two numbers are added is:

  1. a2 b2 + a2 a1 b1 + a2 a1 a0 b0 + a2 a0 b1 b0 + a1 b2 b1 + a1 a0 b2 b0 + a0 b2 b1 b0

  2. a2 b2 + a2 a1 b0 + a2 a1 b1 b0 + a1 a0 b2 b1 + a1 a0 b2 + a1 a0 b2 b0 + a2 a0 b1 b0

  3. a2 + b2 + (a2$\oplus$b2) (a1 + b1 +(a1$\oplus$b1) (a0 + b0))


Correct Option: C
Explanation:

What is the maximum number of different Boolean functions involving n Boolean variables?

  1. n2

  2. 2n

  3. 22n

  4. $2^{n^2}$


Correct Option: C
Explanation:

How many 3-to-8 line decoders with an enable input are needed to construct a 6-to-64 line decoder without using any other logic gates?

  1. 7

  2. 8

  3. 9

  4. 10


Correct Option: C
Explanation:

But we need one more decoder i.e for combining result. 8 + 1 = 9 decoders

Consider the following Boolean function of four variables: f (w, x, y, z) = $\sum$(1,3,4,6,9,11,12,14) The function is:

  1. independent of one variables.

  2. independent of two variables.

  3. independent of three variables.

  4. dependent on all the variables.


Correct Option: B
Explanation:

The control signal functions of a 4-bit binary counter are given below (where X is “don't care”): Clear Clock Load Count Function

The counter is connected as follows:

Assume that the counter and gate delays are negligible. If the counter starts at 0, then it cycles through the following sequence:

  1. 0, 3, 4

  2. 0, 3, 4, 5

  3. 0, 1, 2, 3, 4

  4. 0, 1, 2, 3, 4, 5


Correct Option: D
Explanation:

Define the connective * for the Boolean variables X and Y as: X * Y = XY + X'Y'. Let Z = X *Y. Consider the following expressions P, Q and R.

$\pi P$ : X = Y * Z Q : Y = X * Z R : X *Y * Z = 1

Which of the following is TRUE?

  1. Only P and Q are valid.

  2. Only Q and R are valid.

  3. Only P and R are valid.

  4. All P, Q, R are valid.


Correct Option: A
Explanation:

Suppose only one multiplexer and one inverter are allowed to be used to implement any Boolean function of n variables. What is the minimum size of the multiplexer needed?

  1. 2n line to 1 line

  2. 2n+1 line to 1 line

  3. 2n−1 line to 1 line

  4. 2n−2 line to 1 line


Correct Option: C
Explanation:

Let f (w, x, y, z) = $\sum$(0,4,5,7,8,9,13,15). Which of the following expressions is/are NOT equivalent to f?

P. x’y’z’ + w’xy’ + wy’z + xz Q. w’y’z’ + wx’y’ + xz R. w’y’z’ + wx’y’ + xyz + xy’z S. x’y’z’ + wx’y’ + w’y

  1. P only

  2. Q and S

  3. R and S

  4. S only


Correct Option: B
Explanation:

In a look-ahead carry generator, the carry generate function Gi and the carry propagate function Pi for inputs Ai and Bi are given by:
Pi = Ai $\oplus$ Bi and Gi = Ai Bi The expressions for the sum bit Si and the carry bit Ci+1 of the look-ahead carry adder are given by: Si = Pi Ci and Ci+1 = Gi + Pi Ci, where Co is the input carry. Consider a two-level logic implementation of the look-ahead carry generator. Assume that all Pi and Gi are available for the carry generator circuit and that the AND and OR gates can have any number of inputs. The number of AND gates and OR gates needed to implement the look-ahead carry generator for a 4-bit adder with 3 2 1 0 4 S ,S ,S ,S and C as its outputs are respectively:

  1. 6, 3

  2. 10, 4

  3. 6, 4

  4. 10, 5


Correct Option: B
Explanation:

Given f1, f3 and f in canonical sum of products form (in decimal) for the circuit.

$f_1 = \Sigma m(4, 5, 6, 7, 8)$ $f_3 = \Sigma m(1, 6, 15)$ $f = \Sigma m(1, 6, 8, 15)$

Then f2 is

  1. $\Sigma m(4, 6)$

  2. $\Sigma m(4, 8)$

  3. $\Sigma m(6, 8)$

  4. $\Sigma m(4, 6, 8)$


Correct Option: C
Explanation:

In the IEEE floating point representation, the hexadecimal value 0x00000000 corresponds to

  1. the normalized value 2-127

  2. the normalized value +0

  3. the normalized value 2-126

  4. the special value +0


Correct Option: D
Explanation:

Let $r$ denote number system radix. The only value(s) of $r$ that satisfy the equation $\sqrt{121_r}={11}_r$, is/are

  1. decimal 11

  2. any value >2

  3. decimal 10

  4. decimal 10 and 11


Correct Option: B
Explanation:

If $P, Q, R$ are Boolean variables, then

$(P + \bar{Q}) (P.\bar{Q} + P.R) (\bar{P}.\bar{R} + \bar{Q})$ simplifies to

  1. $P.\bar{Q}$

  2. $P.\bar{R}$

  3. $P.\bar{Q} + R$

  4. $P.\bar{R} + Q$


Correct Option: A
Explanation:

In the Karnaugh map shown below, X denotes a don't care term. What is the minimal form of the function represented by the Karnaugh map?

  1. $\bar{b}.\bar{d} + \bar{a}.\bar{d}$

  2. $\bar{a}.\bar{b} + \bar{b}.\bar{d} + \bar{a}.b.\bar{d}$

  3. $\bar{b}.\bar{d} + \bar{a}.b.\bar{d}$

  4. $\bar{a}.\bar{b} + \bar{b}.\bar{d} + \bar{a}.\bar{d}$


Correct Option: A
Explanation:

What is the minimum number of gates required to implement the Boolean function (AB + C) if we have to use only 2-input NOR gates?

  1. 2

  2. 3

  3. 4

  4. 5


Correct Option: B
Explanation:

(1217)8 is equivalent to

  1. (1217)16

  2. (028F)16

  3. (2297)10

  4. (0B17)16


Correct Option: B
Explanation:

The following is a scheme for floating point number representation using 16 bits.

Bit Position 15 14 .... 9 8 ...... 0
s e m
Sign Exponent Mantissa

Let s, e, and m be the numbers represented in binary in the sign, exponent, and mantissa fields respectively. Then the floating point number represented is:

$$\begin{cases}(-1)^s \left(1+m \times 2^{-9}\right) 2^{e-31}, & \text{ if the exponent } \neq 111111 \ 0, & \text{ otherwise} \end{cases}$$

What is the maximum difference between two successive real numbers representable in this system?

  1. 2-40

  2. 2-9

  3. 222

  4. 231


Correct Option: C
Explanation:

A 1-input, 2-output synchronous sequential circuit behaves as follows: Let zk, nk denote the number of 0's and 1's respectively in initial k bits of the input (zk+nk=k). The circuit outputs 00 until one of the following conditions holds. zk - nk=2. In this case, the output at the k-th and all subsequent clock ticks is 10. nk - zk = 2. In this case, the output at the k-th and all subsequent clock ticks is 01.

What is the minimum number of states required in the state transition graph of the above circuit?

  1. 5

  2. 6

  3. 7

  4. 8


Correct Option: C
Explanation:

The sequential circuit has 3 variables to decide the state in which input & 2 inputs are present. Output for particular inputs decide states.

i/p op 1 op 2 State
0 0 0 Initial
0 0 1 $n_k - z_k = 2$
0 1 0 $z_k - n_k = 2$
1 0 0 Not applicable
1 0 0 Initial
1 0 1 $n_k - z_k = 2$
1 1 0 $z_k - n_k = 2$
0 0 1 $n_k - z_k = 2$
1 1 1 is correct

using 3 bits we require $ 2^3 - 1 = 7 $ states here

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