Which of the following terms is used in cache organisation when the addressed data or instruction is found in the cache during operation?

Which of the following term refers to the translation of main memory address to the cache memory address?

Which of the following level of parallelism is also called fine-grained parallelism?

Which of the following strong consistency models is the one in which if the processes are executed in sequence, then the results are similar to the read write operations?

Which of the following addressing modes in 80X86 is the one in which an effective address is the contents of the base register?

Which of the following operations in pipeline instruction processing is performed first?

Which of the following instruction sets in Instruction Set Architecture (ISA) consists of a variety of expert instructions and may just not be used in practical programs?

Which of the following registers of the vector register processor are linked to the functional units with the help of a pair of crossbars?

Which of the following type of vector instruction is an operation that fetches the non-zero elements of a sparse vector from memory?

Which of the following technique is the one by which the execution of multiple instructions can be overlapped?

Which of the following hazards occur when an instruction depends on the result of a previous instruction in a way that is exposed by the overlapping of instructions in the pipeline?

Which of the following parallelism refers to the way threads can communicate with other threads residing in other processors?

Which of the following principles of multi-threading verifies the number of occurrences of thread switching?

Which of the following interfaces in computer architecture gives a method for transferring information between internal memory and I/O devices?

Which of the following terms in computer architecture is used in each computer having its own particular instruction code format?