If the output of a shift register is fed back to the input, then it is the result of which of the following?

In which of the following modes is 'the datum is in the register' specified by the instruction in 8086 processor?

In which of the following addressing modes, the effective address is the sum of base register and an index register, both of which are specified by the instruction in 8086 processor?

In which of the following modes, 16 bit effective address of the datum is a part of the instruction in 8086 processor?

In which of the following addressing modes, the datum is either 8 or 16 bits long and is part of the instruction in 8086 processor?

Which of the following delays data by one clock time for each stage?

In which of the following logic gates, the output is false only when both the inputs are true?

In which of the following, the contents of IP are replaced by the effective branch address and it may be used only in unconditional branch instructions in 8086 processor?

In which of the following classifications of shift register, the mode control may be multiple inputs, controls parallel loading vs shifting?

In which of the following logics, the output is true only when any one of the inputs were true, and output is false if both inputs are the same logic?

In which of the following, the branch contains the address to be used, if the branch occurs, as two byte following the instruction byte in 8085 processor?

In which of the following, the output is true only when both the inputs are false?

Which of the following can specify the address of the next instruction to be executed, if it is not the one immediately following the branch, in two ways in 8085 processor?

In which of the following logic gates is the output true only when both the inputs were either true or false?

Which of the following modes results in three byte instruction, and first byte contains the instruction itself and second and third byte contain the data, either as a single 8 bit value or 16 bit value in 8085 processor?