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Digital Systems and Microprocessors

Description: Logic design in computer system Digital Systems and MicroprocessorsDigital LogicIT Certificate Programs
Number of Questions: 15
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Tags: Logic design in computer system Digital Systems and Microprocessors Digital Logic IT Certificate Programs
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In which of the following is the effective branch address the sum of an 8 or 16 bit displacement in 8086 processor?

  1. Direct addressing mode

  2. Intrasegment Direct Addressing Mode

  3. Register addressing mode

  4. Instruction

  5. Operand


Correct Option: B
Explanation:

The effective branch address is the sum of an 8 or 16 bit displacement and the current contents of IP in 8086 processor.

If an ADC is subjected to an analog input signal whose frequency exceeds the Nyquist frequency for that ADC, the converter will output a digitized signal of falsely low frequency, then this is called ____________.

  1. step recovery

  2. sample frequency

  3. instruction

  4. ADC

  5. aliasing


Correct Option: E
Explanation:

If an ADC is subjected to an analog input signal whose frequency exceeds the Nyquist frequency for that ADC, the converter will output a digitized signal of falsely low frequency.

Which of the following is used to point to the memory address from where the next byte is to be fetched?

  1. Accumulator

  2. Stack pointer

  3. Program counter

  4. General purpose registers

  5. Control unit


Correct Option: C
Explanation:

The function of the program counter is to point to the memory address from which next byte is to be fetched.

Which of the following is used for temporary store for the current instruction of a program?

  1. Stack pointer

  2. Accumultor

  3. Control unit

  4. Instruction register

  5. Instruction


Correct Option: D
Explanation:

It is used for temporary store for the current instruction of a program.

Which of the following is equal to the one-half of the ADC's sample frequency?

  1. Sample frequency

  2. Nyquist frequency

  3. Step recovery

  4. ADC

  5. DAC


Correct Option: B
Explanation:

It is equal to one-half of the ADC's sample frequency.

Which of the following generates signals within microprocessor to carry out the instruction that has been decoded?

  1. Arithmetic Logic Unit

  2. Accumulator

  3. Stack pointer

  4. General purpose registers

  5. Control unit


Correct Option: E
Explanation:

It generates signals within microprocessor to carry out the instruction, which has been decoded.

In which of the following is the comparator output connected to the inputs of a priority encoder circuit, which then produces an equivalent binary output?

  1. Single Slope Integrated ADC

  2. Flash type ADC

  3. R-2R Ladder DAC

  4. DAC

  5. Step recovery


Correct Option: B
Explanation:

Each of the comparator outputs is connected to the inputs of a priority encoder circuit, which then produces an equivalent binary output.

Which of the following is concerned for addresses that refers to the memory other than registers?

  1. Address range

  2. Address granularity

  3. Register set

  4. Operand

  5. Addressing mode


Correct Option: B
Explanation:

It is concerned for addresses that refers to the memory other than registers.

In which of the following options is the output voltage the inverted sum of all the input voltages?

  1. R-2R Ladder DAC

  2. Binary-weighted input DAC

  3. ADC

  4. Step recovery

  5. Conversion rate


Correct Option: B
Explanation:

The output voltage is the inverted sum of all the input voltages.

In which of the following options is the operand in a memory location and the address of this location is given explicitly in the instruction?

  1. Indirect mode

  2. Index mode

  3. Direct addressing mode

  4. Immediate addressing mode

  5. Address range


Correct Option: C
Explanation:

The operand is in a memory location and the address of this location is given explicitly in the instruction.

A logic circuit which switches between different registers in the set will receive instructions from control unit is called ______________.

  1. register selector

  2. general purpose register

  3. stack pointer

  4. accumulator

  5. control unit


Correct Option: A
Explanation:

Just a logic circuit which switches between different registers in the set will receive instructions from Control Unit.

If an operation involves reference to an operand in memory or available by I/O, then the address of the operand is determined by

  1. operand fetch

  2. operand store

  3. data operation

  4. operand address calculation

  5. fetch instruction


Correct Option: D
Explanation:

If the operation involves reference to an operand in memory or available via I/O, then operand address calculation determines the address of the operand.

Which of the following replaces the contents of IP with part of the instruction and the content of CS with another part of instruction in 8086 processor?

  1. Intersegment Direct Addressing Mode

  2. Instruction fetch

  3. Operand fetch

  4. Direct mode

  5. Immediate addressing mode


Correct Option: A
Explanation:

It replaces the contents of IP with part of the instruction and the content of CS with another part of instruction in 8086 processor.

Which of the following is the time from the instant that an address is presented to the memory to the instant that data have been stored for random access memory?

  1. Transfer rate

  2. Cycle time

  3. Access time

  4. Sequential

  5. Random


Correct Option: C
Explanation:

For random access memory, i.e. the time from the instant that an address is presented to the memory to the instant that data have been stored.

Which of the following requires the DMA controller to arbitrate for the system bus with each transfer?

  1. Single transfer mode

  2. Block transfer mode

  3. Demand transfer mode

  4. Transfer rate

  5. Unit of transfer


Correct Option: A
Explanation:

It requires the DMA controller to arbitrate for the system bus with each transfer.

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