Digital Systems and Microprocessors
Description: Logic design in computer system Digital Systems and MicroprocessorsDigital LogicIT Certificate Programs | |
Number of Questions: 15 | |
Created by: Mira Shah | |
Tags: Logic design in computer system Digital Systems and Microprocessors Digital Logic IT Certificate Programs |
In which of the following is the effective branch address the sum of an 8 or 16 bit displacement in 8086 processor?
If an ADC is subjected to an analog input signal whose frequency exceeds the Nyquist frequency for that ADC, the converter will output a digitized signal of falsely low frequency, then this is called ____________.
Which of the following is used to point to the memory address from where the next byte is to be fetched?
Which of the following is used for temporary store for the current instruction of a program?
Which of the following is equal to the one-half of the ADC's sample frequency?
Which of the following generates signals within microprocessor to carry out the instruction that has been decoded?
In which of the following is the comparator output connected to the inputs of a priority encoder circuit, which then produces an equivalent binary output?
Which of the following is concerned for addresses that refers to the memory other than registers?
In which of the following options is the output voltage the inverted sum of all the input voltages?
In which of the following options is the operand in a memory location and the address of this location is given explicitly in the instruction?
A logic circuit which switches between different registers in the set will receive instructions from control unit is called ______________.
If an operation involves reference to an operand in memory or available by I/O, then the address of the operand is determined by
Which of the following replaces the contents of IP with part of the instruction and the content of CS with another part of instruction in 8086 processor?
Which of the following is the time from the instant that an address is presented to the memory to the instant that data have been stored for random access memory?
Which of the following requires the DMA controller to arbitrate for the system bus with each transfer?