In JK flip-flop, the clock is applied to both flip-flops. The master-slave action is controlled by the Q output of master. The answer is correct.

In 8254, one has to provide the initial value in binary form. This value will provide the required delay. At start, this binary value is loaded to the counter. This is done using parallel-in concept of the shift register. The counter counts down and provides the value to 8254 for comparison with zero. For this, a parallel output stream is used. So, the concept of shift registers is parallel-in and parallel-out.

((A + B)' + C')' = ((A' . B' + C')' = ((A' . B')' . (C')') = (((A')' + (B')') . C) = (A + B) . C

So, this is the correct answer.

The configuration of multiplexer is such that it provides one output at a time depending on the value of select signals from its inputs. This is the correct answer.

The truth table of SUM output of half adder is the same as XOR truth table. So, XOR can be used as a half adder.

One can realise any basic or realised gate using NAND gate only. So, it is a universal gate.

When NOT is connected in between S and R, and S = 1, then R = 0. An applied clock provides output as Q = 1, so D is 1 and Q is also 1. It is the D condition. When S = 0, then R = 1 and the output is Q = 0. This is also the D condition. Other conditions cannot appear. Hence, this configuration will make SR flip-flop a D flip-flop.

If the hardware chip is available, the processor will use it for division. If it is not available, then successive subtraction is used and the hardware used by the CPU is adder (using 2's complement representation).

Propagation delay is the time required by one flip-flop to respond and produce output, and is given as t_pd. In asynchronous counter, the clock is provided only at the first flip-flop. Other flip-flop gets the clock from the Q output of the previous flip-flop. So, time required when the last flip-flop will get the clock is number of flip-flops * response delay of one flip-flop. This total time delay is called propagation delay of the counter. In synchronous counter, all flip-flops get the clock simultaneously.

Yes, this is correct. The output will not change.

When a device is not selected and other device is selected, then the current device must leave the bus, i.e. it should remain open circuited when not selected. The highly resistive output virtually creates an open circuit situation for the device not selected. This feature is not available in normal gates. So, tri-state buffers are required.

Combinational circuits provide output according to current inputs. It does not save or store its output. So, storage capacity is not a part of combinational circuit.

Tri-state buffers provide isolation to the connecting device from the bus when in third state. High resistive feature provides the required isolation.

After completing the function call, the processor returns back to calling program using the address in the stack pointer.

State diagram represents the next stage of a counter.